Conventional non-volatile memory devices have long had problems in overcoming their susceptibility to damage by electrostatic discharge (ESD). Conventional ESD protection structures have been developed for non-volatile memory devices with some degree of ESD protection. For example, lightly doped drain (LDD) implant techniques have been developed to offer some degree of protection against ESD. However, the conventional LDD implant techniques are capable of offering only limited ESD protection and would not be able to meet stringent ESD robustness requirements. For example, it would be difficult for a conventional n-channel metal oxide semiconductor (NMOS) transistor with a lightly doped drain to meet voltage specifications of 2 kV in a human body model (HBM) and 1 kV in a charge device model (CDM).
Conventional medium doped drain (MDD) implant techniques have been developed to increase the ESD robustness of conventional MOS peripheral devices. However, conventional NMOS transistor devices produced by the conventional MDD implant techniques may have high input leakage currents with low breakdown voltages due to shortened channels caused by greatly increased lateral diffusion resulting from the conventional MDD implantation. Since the lateral diffusion may be very fast in a conventional MDD implant process, it may be difficult to control the effective channel length of the conventional NMOS transistors with MDD implant.
Other conventional techniques have been developed to control program and erase characteristics of non-volatile memory devices by applying additional process steps of implantation to change the doping profiles of the sources and the drains of the core memory cells. However, adding process steps to improve ESD robustness of peripheral MOS devices may adversely affect the performance and reliability of the core memory cells.
Therefore, there is a need for a method of improving the ESD robustness of a non-volatile memory device which offers a high degree of reliable ESD protection without an excessive leakage current. Furthermore, there is a need for a simplified process for improving the ESD robustness of a non-volatile memory device without affecting the doping profiles in the core memory cells